The present invention relates to a complex RAIM/ECC design, and more specifically, to method for verifying a complex RAIM/ECC design using a hierarchical error injection scheme.
In a RAIM/ECC multi-channel design that has a large error state space it may be difficult to exhaustively verify the design within the limited time of a machine design cycle. Some ECC designs perform a verification process by randomly flipping a single bit to create correctable errors (CEs), and randomly flipping two or more bits to create uncorrectable errors (UEs) either in a memory location or on a data interface. The RAIM/ECC design has many other error states that requires a more sophisticated error injection scheme. In addition, only a fraction of the state space of bit flips that may result in a single error outcome, for example, a CE may be verified in an allotted time. Another verification scheme is a Reed-Solomon ECC verification scheme which creates patterns by randomly generating a set of test cases with specific parameters.